1. Field of the Invention
The present invention relates in general to electronic devices, and more specifically to a multiple reference clock synthesizer that provides one or more fractional independent clock signals that generated from a single source clock.
2. Description of the Related Art
Many electronic devices use multiple clock signals at a variety of frequencies. A wireless hand-held electronic device, such as a cell phone or the like, uses a different frequency for each of multiple functions, such as a baseband core, digital signal processor (DSP), audio circuitry, video circuitry, USB circuitry, serial communications, etc. It is possible to include a separate phase locked loop (PLL) circuit for each independent clock signal. The multiple PLL solution, however, is not practical for many applications, such as battery-powered, hand-held electronic devices and the like, since each PLL clock circuit uses a substantial amount of space and consumes a considerable amount of power. Also, PLL circuits are mostly implemented with analog circuits which take a significant amount of time to change from one frequency to another. Frequency changes are performed on a regular basis in many hand-held electronic devices to conserve power and maximize battery life, and the delays associated with PLLs are disadvantageous.
It is desired to divide a single source clock by corresponding ratios to generate each of the clocks. Wireless baseband applications, for example, need multiple clocks generated independently for various fractional divide ratios including divide ratios close to 1.